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Design of Power Semiconductor Devices, ES4E8 assignment, 2023/24
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School of Engineering
The University of Warwick
General Assignment Information
Module Code ES4E8
Module Title Advanced Power Electronic Converters and Devices
Assignment Title Design of Power Semiconductor Devices
Assignment
Weighting / Credits
30% coursework / 4.5 CATS
Submission Deadline Noon Thursday Week 21 (22nd February 2024)
Intended Learning Outcomes (ILOs) Assessed
Intended Learning Outcome(s)
(ILOs)
Task / Criterion / Section
LO1: Apply advanced concepts
through the use of device
physics in the context of device
design. [M1, M2, M3, M4, M6]
In this assignment, there are three questions. Please
answer all questions.
Question A [M1, M2, M3, M4, M6]
Question B [M1, M3, M4]
Question C [M1, M2, M4, M6]
Notes:
A total mark below 40% indicates that the ILOs have not all been met at threshold
level;
A total mark in the range 40 – 48% indicates that the ILOs have all been partially met
to at least threshold level;
A total mark of at least 50% indicates that the ILOs have all been met.
Design of Power Semiconductor Devices, ES4E8 assignment, 2023/24
Submission Details
The submission details for this assignment are:
Deadline: Noon Thursday Week 21.
Method: Online submission via Tabula.
Format of submission: A single .pdf file with a meaningful filename that would contain
the student number, the module code, and assignment name, for example:
“1234567_ES4E8_Lab Report.pdf”
Submission length: Maximum 2000 words. You will lose 5 marks per extra page over
the limit.
Formatting instructions: Use a minimum 11-point Arial (or equivalent) font for the text,
with 1.5 line spacing and 25 mm margins all round.
Note: Submissions should be of an appropriate file size and students are responsible for
ensuring that work is uploaded successfully before the deadline. If there are technical issues
when submitting online, please contact the Engineering Student Office
(eng.eso@warwick.ac.uk).
Guidance and Referencing Style
It is serious Academic Misconduct to pass off the work of others (including peers or AI-based
chatbots such as ChatGPT) as your own and you should not permit colleagues to copy from
you. Sources must be appropriately and properly acknowledged every time reference is made
to another’s work, using the Harvard Referencing system. Failure to do so amounts to
plagiarism which breaches university regulations and falls short of the Academic Integrity
expected in the department and university.
Find out more about the School of Engineering Referencing System here:
https://warwick.ac.uk/fac/sci/eng/eso/undergraduate_students/guidance/handbook/skills/s
hb-2-04
There are also other types of academic offences including duplication or ‘self-plagiarism’.
Refer to https://warwick.ac.uk/fac/arts/history/students/undergraduate/assess-plagiarism/
for further details.
Style and Formatting Guide
Submissions are expected to conform to professional standards on style and formatting, and
guidance can be found here:
https://warwick.ac.uk/fac/sci/eng/eso/undergraduate_students/guidance/handbook/skills/s
h-1-06/
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Design of Power Semiconductor Devices, ES4E8 assignment, 2023/24
Assignment Feedback
Your submitted report will be marked electronically. The marks of the various
sections will be provided as well as an outline of the answers of the various sections
in order to identify where/how to improve.
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Design of Power Semiconductor Devices, ES4E8 assignment, 2023/24
Question A
A= (last two digits of your university ID number+350)
B= (last two digits of your university ID number×8+900)
1. Figure 1.1 shows the basic cell structure of a power MOSFET.
Describe the internal resistance components in the power MOSFET on-state operation as shown in
figure 1.2 and comment on their effect as the device voltage rating increases. [5%]
Figure 1.1. Lateral channel power MOSFET – device parameters.
Figure 1.2. Lateral channel power MOSFET – internal on-state resistance components.
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Design of Power Semiconductor Devices, ES4E8 assignment, 2023/24
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Table 1: Device parameters
Variable Value Description
WCELL 22 m Cell width
WC 13 m Contact width
WG 12 m Gate window width
LN+ 4 m n+ source length
Lch 3.5 m Channel length
LA 2 m Accumulation length
WPW 10 m polysilicon width
WS 4 m Source contact width
ρc 7×10-6 cm2 Specific contact resistance
ρSQN+ 10 sq-1 Sheet resistance for N+ source region
XjP 2 m p-base junction depth
XjN+ 0.4 m N+ source junction depth
tox 0.1 m gate oxide thickness
tsub 350 m substrate thickness
ρSI@ Nd=1×1016 cm-3
0.53 cm Silicon resistivity at doping Nd=1×1016 cm-3
ρSI@ Nd=1×1015 cm-3
4.58 cm Silicon resistivity at doping Nd=1×1015 cm-3
ρsub 0.003 cm Silicon Substrate resistivity
ni 1×1010 cm-3
Intrinsic carrier concentration at room temperature
inversion 450 cm2
/Vs inversion layer electron mobility
Accumulation 1000 cm2
/Vs accumulation layer electron mobility
SI@ Nd=1e16 1250 cm2
/Vs Silicon mobility at doping Nd=1×1016 cm-3
SI@ Nd=1e15 1350 cm2
/Vs Silicon mobility at doping Nd=1×1015 cm-3
KA 0.6 Coefficient to account for current spreading from
accumulation to JFET region
Z 500 m length of cell in orthogonal direction to the cross section
ox 3.9 o SiO2 dielectric constant
Np-base 1×1017 cm-3 p-base doping concentration
NDJ 1×1016 cm-3
JFET doping concentration
si 11.7 o dielectric constant of silicon
Design of Power Semiconductor Devices, ES4E8 assignment, 2023/24
2. Calculate the on-state resistance % contribution at room temperature of each internal resistance
component over the total on-state resistance for a “A”V breakdown rated MOSFET @ Vgate=15V,
Vthreshold= 7.5V and Vdrain=0.6V (where the value of “A” is defined above). Identify the most
important resistance contributions.
Use the device parameters as given in table 1 (you may find reference [1], section 6.4 & 6.5 useful for
this analysis). [10%]
3. Calculate the on-state resistance % contribution at room temperature of each internal resistance
component over the total on-state resistance for a “B”V breakdown rated MOSFET @ Vgate=15V,
Vthreshold= 7.5V and Vdrain=0.6V (where the value of “B” is defined above). Identify the most
important resistance contributions and discuss how these compare to your finding in part (3).
Use the device parameters as given in table 1 (you may find reference [1], section 6.4 & 6.5 useful for
this analysis). [5%]
4. Using MATLAB (or analogous software) discuss how the variation of JFET region LJFET (i.e the
distance between the two p-base regions LJFET= 2*LA) affects the performance of the device in part
(2) with specific reference to internal resistance components. Keep the cell width and channel
length constant. Illustrate your answers by means of corresponding plots. [5%]
5. Discuss how a 1.2kV breakdown-rated Silicon MOSFET device would alter the on-state resistance
contributions as the temperature increases from room temperature to 125C°. [5%]
6. Discuss how the 1.2kV breakdown-rated Silicon IGBT structure on-state resistance contributions
differ from those of a 1.2kV Silicon MOSFET. [5%]
References
[1] Book “Fundamental of Power semiconductor Devices” B.J. Baliga, Springer International
Publishing 2008.
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Design of Power Semiconductor Devices, ES4E8 assignment, 2023/24
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Question B
Ambipolar Conduction (aka Conductivity Modulation)
Conductivity modulation is the charge compensation effect that occurs under high level carrier
injection. High level is defined by the rule of thumb that in injection level is > 10% of the background
doping level. Both carrier species are equal, this allows the basic transport equations to be modified
to produce ambipolar transport. Very low resistance bipolar power devices such as diodes, thyristor
and IGBTs use this effect to reduce the on state resistance. Charge is removed slowly by diffusion and
recombination controlled by ambipolar diffusion equation.
Figure 2.1: PiN diode On-state Carrier Density Distribution
The idea here is that under such high-level injection conditions, the two equations for electron and
hole continuity can be combined into a single equation. This means we only need to solve one equation
instead of two. To do this we make the assumption that, we only need solve for on carrier density
since:
p(x) = n(x)
where
2
2 a
a
p p p D
t x

=

Design of Power Semiconductor Devices, ES4E8 assignment, 2023/24
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Where d is distance from the middle of the device (fig.1) and JT is the current density
where
2
n p
a
n p
D D
D =
D D+
Which has the general solution:
( ) ( ) cosh sinh
a a
x x n x p x A B
L L
= = +

Where A and B can be found from the appropriate boundary conditions.
Design of Power Semiconductor Devices, ES4E8 assignment, 2023/24
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Figure 2.2: Simulated silicon PIN Diode
Drift Length = DL= (last two digits of your university ID number×5+80) m
Current Density JT=100A/cm2
Lifetimes: τ = 2, 5, 20 sec
Mobility of Electrons at T=300°K
e=1417 cm^2/(Vs);
Mobility of Holes at T=300°K
p=471cm^2/(Vs) ;
1. Draw a simple schematic a PIN and a Schottky diode and explain what the main differences
between a PIN and a Schottky diode are. [5%]
Given the theory above,
2. Use the analytical equations above to calculate and plot using MATLAB (or analogous software)
the charge concentration across the PIN Diode structure (figure 5) for all three ambipolar
lifetimes values at room temperature. [10%]
3. Use the analytical equations above to calculate and plot using MATLAB (or analogous software)
the charge concentration across the PIN Diode structure (figure 5) for an ambipolar lifetime =
1 s at 75° and 150°C. [10%]
4. Use the analytical equations above to calculate and plot using MATLAB (or analogous software)
the charge concentration across the PIN Diode structure (figure 5) and drift length 2*DL (where
DL is defined above) for an ambipolar lifetime=5 s at 125° C. How doesthis device (drift length
2*DL) performance compare with the previous case (drift length DL) under the on-state and
breakdown conditions [5%].
Anode
Cathode
Design of Power Semiconductor Devices, ES4E8 assignment, 2023/24
Question C
Figure 3.1 shows the on-state characteristics of a 3.3kV Silicon and Silicon Carbide PIN diodes at 25°C.
The blocking Silicon p-n junction consists of a p-type region containing 1019 cm-3 acceptors (NA) and an
n-type region containing of 1014 cm-3 donors (ND). The intrinsic carrier concentration at 300K (25°C) is
1.01 × 1010 cm-3
. Assume that VT,the thermal voltage, (=kB*T/e, where T is the absolute temperature,
kB is the Boltzman constant and e is the charge on an electron) is 26mV at room temperature.
The blocking SiC p-n junction consists of a p-type region containing 1019 cm-3 acceptors (NA) and an n_xfffe_type region containing also of 1015 cm-3 donors (ND). The intrinsic carrier concentration at 300K (25°C)
is 5×10 9
cm-3
.
1. Discuss which type of diode you would use for applications of 50 A/mm2
. (10%)
2. Justify the differences of the two curves given the material properties (i.e. Vo value and
differential resistance (line curvature)) (15%)
3. Discuss which SiC diode type (PIN or Schottky) is preferable for high power applications. (10%)
Silicon
SiC
Figure 3.1: The on-state characteristics of a 3.3kV Silicon and Silicon Carbide PIN diodes at 25°C
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Design of Power Semiconductor Devices, ES4E8 assignment, 2023/24
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Marking Scheme
Class Scale Mark Criteria
100
The appropriate models, correct calculations and/or plots are presented. The
required explanation is accurate and concise. The answer is complete and
correct.
94
The appropriate models, correct calculations and/or plots are presented. The
required explanation is accurate and concise. The answer is complete and
correct but contains 1 minor mistake (unit missing, inaccurate
statement and etc.)
88
The appropriate models, correct calculations and/or plots are presented. The
required explanation is accurate and concise. The answer is complete and
correct but contains 2 minor mistakes (unit missing, inaccurate
statement and etc.)
82
The appropriate models, correct calculations and/or plots are presented. The
required explanation is accurate and concise. The answer is complete and
correct but contains 3 minor mistakes (unit missing, inaccurate
statement and etc.)
78
The appropriate models, correct calculations and/or plots are presented. The
required explanation is accurate but unnecessary long. The answer is
complete and correct but contains up to 2 minor mistakes (unit
missing, inaccurate statement and etc.)
74
The appropriate models, correct calculations and/or plots are presented. The
required explanation is accurate but unnecessary long. The answer is
complete and correct but contains up to 3 minor mistakes (unit
missing, inaccurate statement and etc.). Each 4 minor mistakes
are considered equivalent to 1 error and 1 error is equal to 4
minor mistakes.
68
The appropriate models, correct calculations and/or plots are presented. The
required explanation is in general accurate. The answer is complete but
contains 1 error (wrong statement, wrong formula, inaccurate
plot and etc.). Each 4 minor mistakes are considered equivalent
to 1 error and 1 error is equal to 4 minor mistakes.
65
The appropriate models, correct calculations and/or plots are presented. The
required explanation is in general accurate. The answer is complete but contains
1 error (wrong statement, wrong formula, inaccurate plot and etc.) and up to 2
minor mistakes (unit missing, inaccurate statement and etc.). Each 4 minor
mistakes are considered equivalent to 1 error and 1 error is equal to 4 minor
mistakes.
62
The appropriate models, correct calculations and/or plots are presented. The
required explanation is in general accurate. The answer is complete but contains
2 errors (wrong statement, wrong formula, inaccurate plot and etc.). Each 4
minor mistakes are considered equivalent to 1 error and 1 error is equal to 4
minor mistakes.
First
Excellent 1st High 1st Upper Mid 1st Lower Mid 1st Low 1st
Upper Second (2-1)
High 2-1 Mid 2-1 Low 2-1
Design of Power Semiconductor Devices, ES4E8 assignment, 2023/24
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58
The appropriate model, correct calculations and/or plots are presented. The
required explanation is in general accurate. The answer is complete but contains
2 errors (wrong statement, wrong formula, inaccurate plot and etc.) and up to 2
minor mistakes (unit missing, inaccurate statement and etc.). Each 4 minor
mistakes are considered equivalent to 1 error and 1 error is equal to 4 minor
mistakes.
55
The appropriate models, correct calculations and/or plots are presented. The
required explanation is in general accurate. The answer is complete but contains
3 errors (wrong statement, wrong formula, inaccurate plot and etc.). Each 4
minor mistakes are considered equivalent to 1 error and 1 error is equal to 4
minor mistakes.
52
The appropriate models, correct calculations and/or plots are presented. The
required explanation is in general accurate. The answer is complete but contains
3 errors (wrong statement, wrong formula, inaccurate plot and etc.) and up to 2
minor mistakes (unit missing, inaccurate statement and etc.). Each 4 minor
mistakes are considered equivalent to 1 error and 1 error is equal to 4 minor
mistakes.
48
The appropriate models, correct calculations and/or plots are presented but
some parts are wrong. The required explanation is inaccurate. The answer is
incomplete and may contain up to 1 error (wrong statement, wrong formula,
inaccurate plot and etc.). Each 4 minor mistakes are considered equivalent to 1
error and 1 error is equal to 4 minor mistakes..
45
The appropriate models, correct calculations and/or plots are presented but
some parts are wrong. The required explanation is inaccurate. The answer is
incomplete and may contain up to 2 errors (wrong statement, wrong formula,
inaccurate plot and etc.). Each 4 minor mistakes are considered equivalent to 1
error and 1 error is equal to 4 minor mistakes.
42
The appropriate models, correct calculations and/or plots are presented but
some parts are wrong. The required explanation is inaccurate. The answer is
incomplete and may contain up to 3 errors (wrong statement, wrong formula,
inaccurate plot and etc.). Each 4 minor mistakes are considered equivalent to 1
error and 1 error is equal to 4 minor mistakes.
38
Some of the appropriate model, correct calculations and/or plots are not
presented. The required explanation is very inaccurate. The answer is
incomplete and contains errors and mistakes.
32
Some of the appropriate model, correct calculations and/or plots are not
presented and some are wrong. The required explanation is very inaccurate.
The answer is incomplete and contains errors and mistakes.
25
The appropriate model, correct calculations and/or plots are not presented. The
answer is incomplete and contains errors and mistakes.
Lower Second (2-2)
High 2-2 Mid 2-2 Low 2-2
Third
High 3rd Mid 3rd Low 3rd
Fail
High Fail
(sub
honours)
Fail
Design of Power Semiconductor Devices, ES4E8 assignment, 2023/24
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12
Just initial relevant information provided
0
No answer or irrelevant answer
Low Fail Zero