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of 10Integrated Circuits: Concepts and Design
(ELEC372/472)
Assignment 1 – Hints/Tips
Dr Munira Raja
mraja@liv.ac.uk
ELEC372/472
Design Assignment 1
Write a simple model in Mathcad, Matlab, python or C
a. Fall time as a function of width, W – sensible range of values
b. Fall time as a function of fan-out (i.e. increasing number of inverters to the test
inverter); choose one value of W
You need to about which parameters to define as variables and which as constants; certainly
transistor width (W) needs to be defined as a variable
Make sure you use sensible values for the 1.2 μm technology as used in this course
Complete the Assignment 1 form (deadline on 05/12/2023) available on Canvas
Transient analysis of CMOS Inverter – Fall time
Here CL
is the capacitive loading of ensuing CMOS gates and
also the internal capacitances of the inverter
OV
Vin Vo
C
t = 0
Mp
Mn
V DD
L
90% VDD
10% VDD
Vo
time
In Lecture 6, we derived an analytical equation for the fall time of
an inverter loaded with capacitor CL
At t = 0: input goes high causing Mn to turn on and thus CL
discharges via Mn causing Vo to go low
For t > 0 → derived an expression for the inverter fall time
=

2 0.1

+
2 0.1
0.1
ip ~ 0
=

Set practical values Ln and voltages, and work out the value for CL
Note for this exercise Wn of driver and n (number of fan-out) are variables
K given in script
CGDOn
CGDOp
CGSOp
CGSOn
CG p
CG n
Cdbp
Cdbn
Vi n
Vout Vout2
CW
VD D
Estimating the Load Capacitance CL
Consider unity fan-out and examine components for load capacitance CL
Capacitor Representing
Cgdon Gate drain overlap
Cgdop Gate drain overlap
Cgson Gate source overlap
Cgsop Gate source overlap
Cdb1 Drain body (substrate)
Cdb2 Drain body (substrate)
Cg3 Total gate capacitance
Cg4 Total gate capacitance
CW Interconnect capacitance
CL Combine all above in parallel
Make sure to understand the different capacitive components
Unity fan-out
Definitions of the different capacitive components as
obtained from the SPICE netlist on Multisim
Estimating the Load Capacitance CL
Circuit (CMOS) level
n-well
Capacitor Representing
Cgdon Gate drain overlap
Cgdop Gate drain overlap
Cgson Gate source overlap
Cgsop Gate source overlap
Cdb1 Drain body (substrate)
Cdb2 Drain body (substrate)
Cg3 Total gate capacitance
Cg4 Total gate capacitance
CW Interconnect capacitance
CL Combine all above in parallel
Transistor (nMOS) level
Lateral diffusion
Id (in script)
CGDOn
CGDOp
CGSOp
CGSOn
CG p
CG n
Cdbp
Cdbn
Vi n
Vout Vout2
CW
VD D
Estimating the Load Capacitance CL
W and L are device width and length
Co
is the gate oxide capacitance per unit area
CGDO, CGSO (F/m) = εo
εox ld/tox
(εo = 8.85 × 10-12 F/m; εox = 3.9)
Keqn is a factor that takes account of the voltage dependence
of Cdb related to the capacitance of the depletion region
associated with the drain/substrate junction
SPICE Netlist and parameter tables in the script

=
2
0.025ln
i
D A
bi
n
N N
V

0.5 0.5
0.5
)0.5 (
L
bi H bi L
H
bi
eq V V V V
V V
V
K + +

=
Make sure you understand which
doping region you are looking at
ni
is the intrinsic carrier concentration = 1.5 x 1016 m-3
Capacitor Equation Representing
CGDOn 2 CGDO Wn Gate-drain overlap
CGDOp 2 CGDO Wp Gate-drain overlap
CGSOn CGSO Wn Gate-source overlap
CGSOp CGSO Wp Gate-source overlap
Cdbn Keqn (ADnCJ + PDnCJSW) Drain-body (substrate)
Cdbp Keqp (ADpCJ + PDpCJSW) Drain-body (substrate)
CGn Co Wn
Ln Total gate capacitance
CGp Co Wp
Lp Total gate capacitance
CW Assume to be 1 fF (femto Farad) Interconnect capacitance
CL Combine the above
Parameter Definition NMOS PMOS
Vt (V) Threshold voltage 0.79 -0.91
*Nsub (cm-3
) Substrate doping concentration 2.75 × 1016 1.89 × 1016
*NA
, ND
(cm-3
) Drain/source doping concentration 1 × 1022 1 × 1022
Cj (F/m2
) Zero bias bulk junction bottom
capacitance per m2 of junction area
3.85 × 10-4 4.84 × 10-4
Cjsw (F/m) Zero bias bulk junction sidewall
capacitance per m of junction perimeter
1.39 × 10-10 1.65 × 10-10
ld
(m) Lateral diffusion 1.65 × 10-7 2.2 × 10-8
tox (m) Gate oxide thickness 2.12 × 10-8 2.12 × 10-8
K (A/V2
) Transconductance parameter 9.64 × 10-5 2.94 × 10-5
PS = PD
(m) Perimeter 14 × 10-6 14 × 10-6
AS = AD
(m2
) Area 14 × 10-12 15 × 10-12
Tips/Hints
Select appropriate values for channel width (W) and channel length (L) for both driver and load (note Wn
is a
variable for this exercise which is also linked to the capacitance components). You can express the selected
W and L in terms of minimum feature size m (1.2 μm)
Take into consideration the difference in mobilities of electrons to holes when selecting W and L. Note you
are given the transconductance parameter (μ × Co)
Use appropriate values for VDD and VT
, and as such work out the VH and VL (note for this exercise the VH
is
90% and VL is 10%, however you can compare results with theoretical full range of VH and VL )
Use expressions provided in the script to calculate for each capacitive component (as per table) for
both nMOS and pMOS, using respective parameter values (as per table). Make sure to convert
values in SI units
For calculating Vbi, use correct doping concentration i.e. make sure you understand the region you are
calculating for (i.e. is the doping for an n-well, p-substrate, p+ contact, n+ contact etc)
Resultant CL is simply a parallel combination of the given respective capacitive components
Fan-out analysis
Unity fan-out
~ ~
Fall time:
Last part focused on estimating the value of CL and investigating its
effect on fall-time with changes in W, assuming a unity fan-out (n = 1).
Next part requires to explore the effect of feeding more inverter gates
i.e. n > 1. Note with increase in n, the number of gates increases, and
thus CL will increase
Some capacitance components are larger in comparison e.g. in lecture
assumed for long channels, gate capacitance for instance is more
dominant than interconnect capacitance such that:
=

2 0.1

+
2 0.1
0.1
Device
under test
(DUT)
Fan-out
n
Investigate the dominant capacitance component (note capacitances are in parallel) and examine its contribution to
the overall CL and its effect on the fall-time/rise-time and propagation delays
Set appropriate number of fan-out (n) for same Wn
(can also repeat for different value of W)
Good Luck
35-39
E- to G <35 1 Correct notation used througho ut, wellchosen set of use cases and all case descripti ons present. Good set of use cases but some descripti ons missing or minor case missing or some minor notation problem Poor set of use cases or significant problems with notation. Level of detail not sufficient for problem Some critical use cases missing or use case descriptio ns missing. Shows some correct requirem ents analysis of the problem. No clear evidence that the requirements have been understood at all or no clear attempt at use case diagram or descriptions. 2 All nonfunction elements identified and verificati on explaine d. Good answers but confusio n between function al and nonfunction al requirem ents. Missing one or two nonfunctional requireme nts. Missing up to three requirem ent descriptio ns. Only 2 or 3 correct requirem ents present or incorrectl y defined. Requirements don’t make sense.