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ENT870
Microwave and mm-Wave Integrated Circuit
Design and Technology
Spring Semester 2023
Prof. Khaled Elgaid
ElgaidK@Cardiff.ac.uk
Lecture Notes
All slides/notes can be down-loaded from TEAMS
Enrollment should be automatic
– ENT870
I may make minor updates in lectures – you should hand
annotate the notes
Lecture discussions may deviate from/additional to the
notes.
The course exams includes notes + lectures + practical
assignments/reports
Final Exam 50% + course practical 50%; exam could
include questions from the course practical work
11/04/2023 K. Elgaid 2
Recommend Reading List & Assessment
INDICATIVE READING LIST
Recommended Textbooks:
Introduction to Microelectronic Fabrication, Jaeger, Addison Wesley
Physics of Semiconductor Devices, S M Sze, Wiley 1981
RFIC and MMIC Design and Technology, Ian D Robertson, IET
Background Reading:
VLSI Fabrication Principles, S K Ghandi, Wiley 1983
VLSI Technology – S M Sze
ASSESSMENT
Final Written Examination Contribution 50 %
Semester of Examination End of Spring Term
Duration of Examination 2 hrs
Practical 50%
11/04/2023 K. Elgaid 3
What is a Semiconductor
Conductor – No Gap : electrons free to move between the Valence and Conduction Bands
Insulators – electrons unable to cross the forbidden gap without large energy input
Semiconductor – electrons can cross gap with small amount of energy input
Conduction Band
Conduction Band
Band
Conduction Band forbidden gap
Gap
Valence Band Valence Band
Valence Band
Energy Conductor Semiconductor Insulator
Heat
Light
Electricity
4
Direct & Indirect Band Gap
Conductive Band Electron
Hole
X
Band Phonon-Electron
Gap
interaction
X
Phonon can give and
Valence Band take energy from an
Energy electron
Direct Indirect
In an “indirect” gap, a photon cannot be emitted because the electron must pass through
an intermediate state and transfer momentum to the crystal lattice
5
Where are the elements semiconductors
Single element semiconductor – composed of a single element; Group IV elements
compound semiconductor – composed of two or more elements
Groups III & V, II & VI.
The common feature to all of these is they have an average of 4 valence electrons per atom.
Examples of compound semiconductors – gallium arsenide (GaAs), gallium nitride
(GaN), indium phosphide (InP), and silicon carbide (SiC).
6
Most used Compound Semiconductors for
Electronic devices
Material Direct / Band Gap Benefits
Indirect Energy at
Bandgap 300K(ev)
Elements Si Indirect 1.12 Low cost, Medium/high frequency, low
power, integration, large wafers
Group GaAs Direct 1.42 High speed, medium power, low cost
III-V InAs Direct 0.36
Compounds InSb Direct 0.17
GaP Indirect 2.26
GaN Direct 3.36 High power, high frequency
InP Direct 1.30 High speed, low noise, low power
GaO Indirect/Dir 4.8 Low Frequency High Power TX/RX
ect High Power Switch – Thousands of volts
Group SiC Indirect 2.99 High power, Low frequency
IV-IV
compounds
Group ZnO Direct 3.35
II-VI CdSe Direct 1.70
compounds ZnS Direct 3.68
7
Technology Performance Comparison
Technology Performance Comparison – Why GaN
Performance of GaN compared to Si and GaAs
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Example of Active Devices – Is it GaN on SC or GaN on Si
Substrate Substrate Cost Thermal RF signal Residual strain
conductivity Substrate at RT
￡/cm2
Losses
W/cmK (Wafer Level)
SiC 10 4.2 ~ 1.5dB/mm Close to zero
@60GHz
Si 0.1 1.5 LR Tensile
> 20 dB/mm
GaN/SiC substrates are manufactured by only a handful of companies at prices
prohibitive to volume production, but offer great potential for high-performance
devices.
So by using Compound Semiconductor GaN on Silicon substrate we get advantages
GaN high-performance with the cost saving of a silicon substrate; but more
fabrication steps challenges for the RF applications!
10
What is Required to Develop SC Integrated Electronic
Circuits
Micro/Nano Technology and Nanofabrication
Micro & Nano Technology
– Engineering at the micro/nano-metre scale to
improve the performance of the products and
enable new technology/applications
Micro/Nano-fabrication
– Techniques to fabricate micro/nano-metre
scale devices, components and systems
11
Nano/Micro Application Pull / Technology Push
M
W,
m
N N O
a n o f a b r i c a ta i on no e l e c t r o nm i c s- W a v e &p t To He l ze c t r o nB i ci o st e c h n o l o g yS e n s o r
s
M EM Mi c r o f l u i d i
c
s
S
Defence & Security
Energy
Environment
Healthcare
Supporting science
Manufacturing
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Examples of CS & Si Chip Technology
13
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Active Layer – made by
Buffer – made by MBE or
MBE or MOCVD – Not
MOCVD – Not required
required in Si CMOC
in Si CMOC
Thickness ~ few μm
Thickness ~ few μm
Substrate – made by Czochralski growth method
Could be mad of Si or CS ~ 500μm
Examples of CS & Si Chip Technology
Molecular Beam Epitaxy (MBE)
Czochralski growth
Metalorganic Chemical
Vapour Deposition
14
(MOCVD)
Examples of CS & Si Chip Technology
Czochralski growth
CMOS Si
Czochralski growth + Diffusion or Ion Implantation
GaAs, InP etc..
Czochralski growth is used to make the substrate only
15
Examples of CS & Si Chip Technology
16
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Molecular Beam Epitaxy (MBE)
MBE Ultra High Vacuum
(UHV) conditions (ie
pressures below 10-8 Torr)
Examples of CS & Si Chip Technology
17
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Metalorganic Chemical Vapour Deposition (MOCVD)
In contrast to molecular-beam epitaxy (MBE), MOCVD growth of crystals is by
chemical reaction and not physical deposition; In MOCVD reactant gases are fed into
the system at high pressure ~ 1 torr
Active devices – a brief overview
§ Field effect devices
i.e. GaAs, GaN and InP High Electron Mobility Transistors (HEMTs)
Advanced silicon-on-insulator (SOI) metal-oxide-semiconductor
CMOS
§ Bipolar devices
Si Bipolar Junction Transistors (BJT)
SiGe Heterojunction Bipolar Transistors (HBT)
GaAs and InP Heterojunction Bipolar Transistors (HBT)
11/04/2023 K. Elgaid 18
CS Technology Topology – Transistor
19
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Lateral Device
Ids
Igs
Source Gate Drain Verticle Device
Emitter
Base
Depletion
a
h
Region
Channel
Field Effect Transistors (FET)
n+
Uni-Polar Depletion
p
Regions
Schottky gate – III-V
n-
MOS gate – Si
Collector
Drain
Gate Bipolar Transistors
Collector
Source
Base n+ p n-
Emitter Emitter Base Collector
How Transistor Work – DC Mode
20
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V
DS
Vds = 0
V
gs
Vgs = 0
Source Gate Drain Id = 0
Depletion
a Region
h
V
DS
Channel
V
gs
Drain
Source Gate
Vds > 0
Vgs < VT a h V Id > 0 DS
Channel
V
gs
Source Gate Drain
Vds > 0
Vgs > VT a
h
Id = 0 Channel
How Transistor Work – RF Mode
21
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Lateral Device
Ids
Igs
Source Gate Drain
Depletion
a
h
Region
Channel
Schottky gate – III-V – Field Effect Transistors (FET)
Technology Topology – Transistor
22
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Oxide or Schottky Contact
Scientific Reports
23
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Lateral Technology Topology – Transistor – CS
Lateral Device
Depletion
Enhancement
GaN power devices need comparatively low gate-source voltages to operate
Full enhancement of the device channel ~ 5 V Vgs
Important to not overdrive the gate; ~ 6 V maximum
GaN Electronic Devices Applications – Transistors
24
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RF GaN HEMTs Power GaN HEMTs
– High Gain – High Power
– Low Noise – Good Thermal
– High Power – Operating Voltage up ~ KV
– High Efficiency
– Good Thermal
– Operating Voltage
Generally What is the difference in technology
Small Signal Model for a FET
Active devices
Field effect transistors (FET) at RF
Ids
Igs
Source Gate Drain
Depletion
a
h
Region
Channel
Active devices
Field effect transistors (FET) – f
T
g
m
f =
T
2p(C + C )
gs gd
Similar form of expression to that for bipolar device
If all parasitics (frequency dependence) are included expression is modified to
For mm-wave and sub mm-wave frequencies – important
g
f = m
T ‘ ! $ *
R + R
2π)( C + C ) #1+ s d &+ g C (R + R ) ,
gs gd m gd s d
R
( ” % +
ds
Fabrication scale; What is a nanometre
“Nano” is the Greek word for “dwarf”
1 nanometre = 1 nm = 1 billionth of a metre = 10–9 m
1 nanometre = 1/ 70,000th the diameter of a human hair
1 nanometre = 4 times the diameter of a silicon atom
Example; The gate length in silicon
transistors metal
inside laptops is 35 nm
Example; The gate oxide in silicon
silicon
transistors
1i1n/0s4/i2d02e3 laptops is 1.2 nm thick vertiKc.a Ell gaid Core 2 Duo transistor 28
Example of Transistor Gate Lengths in Computers; Si Technology
80
70
60
50
40
30
20
Year
)mn(
htgneL
etaG
rotsisnarT
35 nm
15nm
10nm
11/04/2023 K. Elgaid Images from29 Intel
Active devices
Requirements for high MAG / f
max
All requirements for high f plus
T
– Low gate resistance
Low gate resistance together with short gate
length requires the so called T-gate
Large
Small
cross-sectional
footprint
area
How Gate Length (Lg) related to f (GHz) Performance
T
11/04/2023 K. Elgaid 31
Advantages of short gate length
– RF
Higher operating frequencies
Higher device gain
Lower noise figure
New applications
– VLSI (CMOS)
Less supply voltage (VDD) requirements
Less input capacitance
Less delay
Higher speed Clock
Less power consumption
11/04/2023 K. Elgaid 32
MMIC Technology Issues
o Performance
EPI Layer
Substrate
Fabrication
Modelling
Design
Packaging
o Reliability
EPI Layer
Fabrication
operating conditions
Utilization Environment
o Cost
EPI Layer
Substrate
Fabrication
Modelling
Design
Packaging
33
Technology requirements to develop MW, mm-Wave & THz ICs
MMIC 3D View
Interdigitated Coplanar Waveguide Coplanar Waveguide
Capacitor (2nd level metal) Groundplane (2nd level metal) Transmission Line
Coplanar Waveguide (2nd level metal)
Transmission Line
(2nd level metal)
Airbridge
(3rd level metal)
Drain
Gate
Source
High FrequencyElectronics
Thinm filmHEMT-based MMIC Process
metal resistor
(resistor metal)
MMIC –MonolithicMicrowaveIntegrated Circuit
Metal-insulator-metal
HEMT capacitor METG mHEMT
(isolation, Ohmic metal, gate metal, 2nd level metal overlay) (1st level metal-dielectric-2nd level metal) GATE
SiN
SiN
MET1 OHM MESA MET1 NiCr
SUBSTRATE (GaAs 4“)
Au
! Twometallizationlevels ! SiNPassivation
! Airbridges ! Full-wafer 50 μm backside process
! MIM capacitors ! Coplanar and microstriplines 34
! NiCrresistors
Fraunhofer IAF 6
III-V HEMT Based Coplanar Waveguide MMIC
Simplified Process Flow – no via
Parasitics Technology Challenges
segnellahC
ygolonhceT
taeH/rewoP
GaN Market : Frequency of interest, technology and design
challenges
Toward mm-wave & THz Applications
mm-wave & THz
Radar, Imaging
Wireless
& Sensing
backhaul
36
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Frequency of interest, technology nodes
Ids
Igs
Source Gate Drain
a Depletion
h Region
Channel
~ 0.1um gate ~ 50– 20nm gate
~ 10nm barriers ~ 5 – 2nm barriers
Scaling Challenges – Applications – Market – Comprehensive Solution – Emerging
37
Technologies
Challenges due to heath & substrate parasitics
Heath
Surface wave and leaky waves (Coupling Capacitance)
Attenuation
HEMT
Surface Wave
Heat
Coupling Capacitance
38
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Challenges due to LR/Thick Si Substrate for Active
Heath
Surface wave and leaky waves (Coupling Capacitance)
Attenuation
HEMT
Surface Wave
Heat
Coupling Capacitance
39
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Challenges due to Si Substrate – RF Signal Attenuation
Substrate RF Signal Substrate Losses
SiC Loss 1.5dB/mm (60GHz)
Si Loss > 20 dB/mm (across all the frequencies)
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40
6G Wireless Communications Challenges
3G 4G 5G 6G
3 Mbps 100 Mbps 10 Gbps 1 Tbps
200’s 2010’s 2020,s
RF Devices Requirements – HEMT
More Output Power
Power density
More Bandwidth
Challenges
Higher efficiency
41
Wireless Communications Demand
Cellular network operators begin to switch on and deliver the 5G experience to meet
global connectivity demands, now we are moving to 6G to meet the future wireless
connectivity demands
11/04/2023 K. Elgaid 42
The power consumption of a typical 5G telecom site
6G will need more power than 5G
About 70 percent increase in power
requirements as switching from 4G to 5G
4G base station consumes around 7 kW of
power
5G base station will need in excess of 11 kW
For a site that carries multiple channels this
could reach 20 kW.
As a 3 kW 48 VDC is industry standardized on power supplies
With 6G total power requirements will increase significantly (5G doubles)
Need to increase the power density significantly in order to deliver more power in
the same footprint using predominantly the same infrastructure
Also end devices power consumption will increase
43
Bristol University
6G Wireless Communications Challenges
3G 4G 5G 6G
3 Mbps 100 Mbps 10 Gbps 1 Tbps
200’s 2010’s 2020,s
RF Devices Requirements – HEMT
……….HEMT Device efficiency
Challenges
Higher efficiency
……. lower operating temperature
……..Power density
……. lower patristics MMIC
……..Surface-mount device packaging (SMD)
The only to address this design challenge is to increase the efficiency of the power conversion
stage
Two technologies can make this possible (delivering greater power output in the same
footprint), GaN and SMD packaging
44
Cooling GaN further, Introducing Heath Sink
45
GaN Devices Substrate Issues – Transistors
46
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GaN device on membrane, Si etch and replace it with heat sink
Exploitation of the Electro-Magnetic Spectrum (RF)
Wireless communications
47
MW, mm-Wave & THz Applications Using Micro/Nano Technology
MW, mm-Wave & THz frequencies
exploitation in the MHz – 1THZ Spectrum
11/04/2023 K. Elgaid 48
11/04/2023 K. Elgaid 49
From Concept to Product I – mmWave
EXAMPLES: Generic frontend TX/RX topology
System Design
&
Specifications
Sub-
system
Design
Layout
Design
Motivation
One platform technology
Wafer
Integration
Fabrication
Low Loss components/substrate
&
High Power
Chip
Array dicing
Packaged diced chip
11/04/2023 K. Elgaid 50
i.e. FMCW Radar (IAF)
From Concept to Product II – Microwave (low frequency end)
INTEGRATED CIRCUITS (lower Frequencies)
Wafer level
Die or chip
Metal lead frame
Metal die frame Bond wire
Package leads or pins
11/04/2023
K. Elgaid 51
From Concept to Product III
System/subsystem specification
Chip specification
– i.e. power, noise, gain, linearity, functionality, ￡￡￡ cost,… !
Chip Technology
– i.e. Silicon or Compound Semiconductor
Schematic design
Chip Layout design
Chip Fabrication
Chip Testing
Chip Packaging
11/04/2023 K. Elgaid 52
Closely Coupled Core Technologies Development
Required –Example – CHFE Team at CU
Characterisation LAB
Wafer
Growth
FAB
CHFE at ICS
Know-how of a diversity of FAB process
53
Technologies Devices
Full MMIC Development
Prototype/concept
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Potential
Technology Transfer
Examples of Microstrip and Coplanar
Waveguide ICs
Microstrip IC Coplanar Waveguide IC
54
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Civil use wireless telecommunications world: Technology Key
Elements
55
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We all want higher Data Rate, Transmission Range,
Smaller Chip, Lighter weight & Lower Cost- 5G
How
Higher operating frequency
Higher integration level
Higher Output Power & Higher Device Efficiency
Lower Noise
Good Heat dissipation
But cost is the deciding factor – Horses For Courses
Radar, and Space: Technology Key Elements
56
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We all want – Higher Resolution, Integrated, Transmission
Range, Smaller Chip, Lighter Weight & Lower Cost-
systems
How
Higher operating frequency
Higher integration level
Higher Output Power & Higher Device Efficiency
Lower Noise
Good Heat dissipation
Higher response to signal detection
Reliability/Lifetime
But NO cost deciding factor – High end technology
Technology requirements to develop MW, mm-Wave & THz
circuits
Components make the Monolithic Integrated Circuit
– Transistors – Active Device
– Diode
– Capacitors
– Inductors
– Transmission media (interconnect)
– Resistors
– Other passives, i.e. couplers, dividers, integrated antennas,
etc…
57
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CS Integrated Circuits Interconnect Technologies
Signal
Microstrip (MS) Substrate – Dielectric
Ground
Signal
Ground Ground
Substrate – Dielectric
Coplanar waveguide
58
Impedance of transmission lines depends on
– track width and height
– substrate thickness
– substrate permittivity
– operating Frequency
Zo ~ square root L/C
100
80
60
40
20
0
0 20 40 60 80 100 120 140 160
Track width (μm)
)W(
ecnadepmI
w
t
h
e
r
200 μm substrate
150 μm substrate
100 μm substrate
e = 12.9
r
track thickness = 2 μm
)W(
ecnadepmI
Microstrip – some details
e = 12.9
r
54
track thickness = 2 μm
53 200 μm substrate
52
51
100 μm substrate
50
49
10 20 30 40 50 60 70 80
Frequency (GHz)
59
Impedance of transmission line depends on
g w g
– track width : groundplane spacing
t
– substrate permittivity
e
h r
– substrate thickness (but not strongly)
– Operating Frequency
100
80
60
40
20
0
0 20 40 60 80 100
)W(
ecnadepmI
56
10 μm track width
55
54
20 μm track width
53
52
30 μm track width
51
50
e = 12.9
r
track thickness = 2 μm 49
48
10 20 30 40 50 60 70 80
gap width (μm)
)W(
ecnadepmI
Coplanar Waveguide (CPW)- some details
e = 12.9
r
track thickness = 2 μm
10 μm track width
30 μm track width
60
Frequency (GHz)
Performance issues of conventional interconnect
GCPW – 2
CPW MS
MS
GCPW
GCPW – 1
§ GCPW 1 Via to via spacing
X: 75 μm , Y: 150μm
§ GCPW 2 Via to via spacing
X: 75μm , Y: 75μm
The GCPW via distances < λ/4 and close to the edge of ground plane Signal Better results (left) Ground Ground for the best parasitic suppression Substrate - Dielectric Interconnect Technology Standard Microstrip (MS), ground plane on back of 50μm Substrate – Dielectric loss – Dielectric constant – Large inductance of via Coplanar Waveguide (CPW) – Packaging issues – Airbridages capacitance Grounded Coplanar Waveguide (GCPW) – Dielectric loss – Moding at the substrate, function of via spacing and operating frequency Air-Bridged Coplanar Waveguide (AB-CPW) Top surface Shielded Microstrip – Low dielectric loss & Low dielectric constant – Can be used for low resistivity substrates, i.e. GaN on Si; substrate independence – No via inductance issues, only 10 micron via depth – Suitable for packaging – Conventional CPW transmission line Centre conductor Ground plane Substrate S W S Propagation region of EM wave Substrate dielectric loss Limited usable impedance ranges Impedance range 30-80 W CPW Impedance Extremes Wide gap between ground and centre line S High Z line Narrow centre line 0 W S High conductor loss Problem: impedances outside the range One solution: concept of elevated CPW of 30-80 W cannot be fabricated reliably and air substrate thin film microstrip lines S Narrow gap between ground and centre line Low Z line 0 W High current density at conductor edges S Elevated CPW (ECPW) Lines Elevation of ground plane Elevation of centre conductor and centre conductor Elevated centre conductor CPW Elevated Ground plane ground plane Metallic post Metallic Elevated centre post GaAs substrate conductor GaAs substrate Propagation region of EM wave Propagation region of EM wave ECPW Lines Elevation of ground plane Elevation of centre conductor and centre conductor 100 μm long air-bridge sections - posts 15 x 15 μm2, height 5 μm Elevation of propagation of EM wave Impedance varied by adjusting W and S Separation from substrate Low loss over wide Z range 0 Reduction of substrate loss Good candidate for to 200 W at a lower loss Widening of centre conductor to reduce loss factor than standard CPW Widening of centre conductor to reduce loss Air Thin Film Microstrip Line (TFMS) TFMS line Ground plane Metallic post GaAs substrate Rectangular slot Reduced dielectric loss ( air dielectric) Reduced ohmic loss - very wide lines for a given line impedance Dispersion free transmission lines Good candidate for low Z down to 1 W 0 Measured Loss Factor 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 0 10 20 30 40 50 Frequency (GHz) Loss factor of high impedance elevated CPW ￡ standard CPW line rotcaF ssoL 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 0 10 20 30 40 50 Frequency (GHz) rotcaF ssoL Characteristic impedance 50 W Characteristic impedance 90 W Series/Shunt CPW Impedance Extremes Series CPW stubs Shunt CPW stubs W High Z S W S Large conductor loss 0 stub S S Problem: serious limitation in realizing low or high impedance levels series/shunt stubs with S S conventional CPW Low Z 0 W High current density at W stub S S conductor edges Concept of Elevated CPW/Thin film series and shunt stubs High impedance series Low impedance series EC-CPW stub “Air TFMS” stub Center conductor of Center conductor Ground plane “Air TFMS” EC-CPW series stub of CPW line of CPW line series stub Metallic post Ground plane Center conductor of CPW line of CPW line GaAs substrate Rectangular slot Low loss over a wide range of high Dispersion free series stub impedances series stubs Reduction of the substrate dielectric loss High characteristic impedance up to 200 W Low characteristic impedances down to 1 W Low impedance shunt High impedance shunt “Air TFMS” stub “Air TFMS” stub Center conductor Center conductor “Air TFMS” of EC-CPW line “Air TFMS” of CPW line shunt stub shunt stub Metallic Metallic post post Rectangular Rectangular Ground plane slot slot Ground plane of EC-CPW line of CPW line Dispersion free shunt stubs Reduction of the substrate dielectric loss Experimental validation 0 -5 -10 -15 -20 -25 -30 -35 -40 0 5 10 15 20 25 30 35 40 Frequency(GHz) )Bd( sretemaraP-S 0 S21 -5 S11 -10 -15 -20 -25 -30 -35 -40 0 5 10 15 20 25 30 35 40 Frequency (GHz) )Bd( sretemaraP-S High impedance series Low impedance series EC-CPW stub “Air TFMS” stub S21 S11 These two proposed series stubs behave as standard series stubs 0 -5 -10 -15 -20 -25 -30 -35 -40 0 5 10 15 20 25 30 35 40 Frequency (GHz) )Bd( sretemaraP-S 0 -5 S21 -10 -15 S11 -20 -25 -30 0 5 10 15 20 25 30 35 40 Frequency(GHz) )Bd( sretemaraP-S Low impedance shunt High impedance shunt “Air TFMS” stub “Air TFMS” stub S11 S21 These two proposed shunt stubs behave as standard shunt stubs Size Reduction of “Air TFMS” stubs using series loading Principle Original transmission line Series loading Inductive load Zo = Zo×sin(θ ) 1 1 Z < Z Reduced size 01 o transmission line q < l/4 1 1 1 Zo L = cos(θ ) 1 ω Lumped element loading Transmission Line Length Reduction Proposed THz-MIC Passives/Interconnect Technology Challenges due to thick, high dielectric constant ( ~12) and LR Substrate: r § Surface wave and leaky waves § Back radiation § Attenuation § Large via inductance § Airbridages capacitance Top surface Shielded Microstrip is required Top surface Shielded Microstrip Low dielectric loss Low dielectric constant Thick film thickness MMIC Fab Compatible ` THz-MIC Interconnect Technology Top surface Shielded Microstrip 1mm Line with probe pads (500GHz – 750GHz) - Loss (S21) < 1.5 dB/mm @ 67 GHz & < 3dB at 750GHz with excellent match Various forms of Transmission Lines Two wire Microstripe Coaxial cable line cable Rectangular Circular Stripline waveguide waveguide Coplanar waveguide Characteristic Impedance Z 0 Skin effect Electric field (E) & Magnetic field (H) Attenuate in conductor The skin depth: Thickness where these fields are fallen to 1/e ~ 37% @ 5 * skin depth - the fields can be considered to be 0 (The actual value is ( 1/e )^5 = 0.674 %; which, is quite small ) 2 d = wμs The figure shows a good conductor and how a pulse traveling along this conductor is attenuated going into the conductor Transmission line lumped element equivalent circuit practical purposes we can ignore the contributions of R' and G' Characteristic impedance does not even need a transmission line, there is a characteristic impedance associated with wave propagation in any uniform medium. In this case we use the eta for impedance. The intrinsic impedance is a measure of the ratio of the electric field to the magnetic field. Impedance of free space use 377 ohms for the characteristic impedance of free space in most calculations involving atmospheric propagation A few final notes about Microstrip and CPW Microstrip – Relatively well behaved electromagnetic environment – Via-holes to ground - series inductance – Wafer thinning – Dispersive at mm-wave frequencies Coplanar waveguide – Airbridges to suppress slotline mode – Complex electromagnetic environment – No wafer thinning required (at least to around W band Frequencies ~ 90GHz) – low dispersion at mm-wave frequencies Passive Element Realisation and models Resistors Thin metal film, Current flow layer of semiconductor or polysilicon W C s s R = R + 2R sh c W L R R - the sheet resistance of the metal film sh or doped semiconductor region s - the separation between contacts defining the length of the resistor parallel to current flow W - the width of the resistor in the direction perpendicular to current flow R - the resistance of the contact at either end of the structure c Capacitors Metal-insulator-metal capacitors C Second Metal First Metal L R G Substrate Insulator (Si N , polyimide) 3 4 Plate areas : 10 - 150 μm2 top-plate area : A Dielectric thickness :150 nm (SiNx) dielectric permittivity : e r 10 μm (polyimide) dielectric thickness : d Capacitor values : 0.1 - 50 pF C Passive Element Realisation and models Passive Element Realisation and models Si3N4 MIM Capacitors Deposition 5nm – 150nm Highly Uniform Effective Perimtivity ~7.5 Width Width Length Length LAYOUT of SHUNT CAPACITANCE in CPW LAYOUT of SERIES CAPACITANCE in CPW Passive Element Realisation and models Capacitance Density 20 μm wide MIM capacitors with SiNx deposited at 22C 8 7 6 5 4 3 2 1 0 0 10 20 30 40 50 60 )Fp( ecnaticapaC 5 nm SiNx 120 nm SiNx Capacitor Length (μm) Density = 7 fF/μm2 k = 7.5 5 nm SiNx ~ 2.5 nm EOT CAPACITANCE vs. AREA for 120nm THICK SI3N4 DEPOSITED at 25C (CAPACITANCE WIDTH 20μm) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 10 20 30 40 50 60 70 CAPACITNCE LENGTH (μm) )Fp( ECNATICAPAC Passive Element Realisation and models Si N MIM Capacitors 3 4 120nmSERIES CAPACITNCE (pF) 120nmSHUNT CAPACITNCE (pF) RES ID=R1 R=210000 Ohm TLINP TLINP ID=TL1 ID=TL2 Z0=50 Ohm Z0=50 Ohm L=260 um L=260 um PP =O 1R T LE oe sf sf == 76 0. 09 IC DA =P C1 LE oe sf sf == 76 0. 09 Z=50 Ohm F0=60 GHz C=0.11 pF F0=60 GHz PORT P=2 CAP IC DA =P C3 Z=50 Ohm ID=C2 C=0.0015 pF C=0.0015 pF Passive Element Realisation and models Capacitors II [3] 125 Interdigitated Capacitors Measured 100 Calculated ) s F f 75 ( e c n a t 50 i c a p a C 25 w 0 0 50 100 150 l (μm) R (kΩ) cap l e r +1 L p (pH) R series (Ω ) C(pF) = l[(N -3)A + A ] 1 2 w A1 (pF) = 8.85x10-12 w w in cm R d(k Ω ) C (pF) A2 (pF) = 9.92x10-12 w C prime (pF) p R d (k Ω ) Capacitor values : 10 - 100 fF C (pF) p Passive Element Realisation and models Inductors C L R C C para para Inductor range 1 - 20 nH Q up to 25 Self-resonant frequency 10 - 40 GHz Cardiff University MSc Design Map 11/04/2023 K. Elgaid 90 On-wafer Shunt Capacitor Measurements 11/04/2023 K. Elgaid 91
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