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CMOS Design Assignment (2025)
You are required to design a simple CMOS circuit consisting of a two-input NOR gate. You
are required to show the layout (plan view) of the circuit, after calculating the aspect ratio
(W/L) of the transistors. The layout of the circuit should include the VDD and ground lines.
Marks will be awarded for the calculations, the explanation of the calculations, the layout, and
the quality of the drawing of the layout. You must also upload, with the layout, a summary of
your calculations with full explanation.
Specification:
VDD = 5 V, threshold voltage of n- and p-channel MOSFETs are VTn = 0.2 V, VTp = -0.2 V
respectively, oxide capacitance Co = 5×10-4 Fm-2
, electron mobility 0.1 m2
V-1
s-1
, hole mobility
0.05 m2
V-1
s-1
, minimum feature size L=2l=0.2 μm, alignment error l=0.1 μm. The area of the
circuit should be a minimum.
Understanding alignment error (l) and minimum feature size (L):
The minimum feature size is the smallest dimension that can be defined on a chip. This
will often be the channel length L.
The various layers have to be aligned (registered) with each other. This involves some
error in placing any mask relative to the pattern already on the silicon. It is necessary
to know how large (in microns) the error can be. You must allow for this in the design.
Your notes in Lecture 9 give you necessary information for following l-rule when
drawing your design.
The assignment (maximum four A4 pages) is due
on Friday 4th April 2025.
After this date, 5% will be deducted for each day that it is late.