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ELEC372/472 – Assignment 3 1
ELEC372/472: Integrated Circuit Design Assignment 3
Objectives:
To understand the fundamental concepts underlying the behaviour of an operational amplifier
(Op-amp) as covered in ELEC372/472 in the context of design.
To design a single-stage Op-amp using a 1.2 μm CMOS technology with specified input and
output conditions. This requires initially calculating the aspect ratios of all transistors in the
design, followed by simulating the design on MultiSim, and verifying key findings to those in
the specification.
To design and simulate a two-stage Op-amp by introducing a common-source stage and a
compensation capacitor to the above design. The aspect ratios will need to be recalculated,
and the design simulated on MultiSim, with key outputs verified to those in the specifications.
For guidance, a 15-credit module unit is meant to occupy 150 hours in total (including both private
study and contact hours). You should aim to spend about 3-4 hours per week at the terminals. The
remainder of the time will be taken up with background reading and research.
KEEP A LOG BOOK OF YOUR PROGRESS.
EFFECTIVE TIME MANAGEMENT IS A KEY SKILL THAT APPLIES TO ALL
PROFESSIONS AND WORKING SITUATIONS.
SO IF YOU GET STUCK, ASK – DO NOT WASTE TIME – STAY FOCUSED
Any queries on the assignment, email:
Dr. K. Hoettges at k.hoettges@liverpool.ac.uk
ELEC372/472 – Assignment 3 2
Introduction
Operational amplifiers (Op-amps) are key building blocks used in digital and analogue systems to
increase the current, voltage or power of an input signal. The simplest single-stage Op-amp circuit
design is shown in Fig.1, comprising of a:
a. Differential pair (nMOSTs: M1 and M2). A differential amplifier amplifies analogue and
digital signals and offers an output in response to the differential inputs (Vin1 and Vin2). The tail
of the differential pair is biased by a DC supply current source i.e. Io represented by Mo, Mbias
and Ibias, which ensures that the circuit always operates in saturation. Typically, the aspect
ratios of M1 and M2, and Mo and Mbias are the same respectively.
b. Current mirror (pMOSTs: M3 and M4). A current mirror copies a current through one active
device by controlling the current in another active device regardless of loading. In the circuit,
M3 is always saturated i.e. its drain and gate terminals are tied (or VDS = VGS – VT). As M3 and
M4 have a common gate i.e. VGS are identical, then the current through M3 and M4 would be
the same if the dimensions are identical i.e. the current in the two transistors are mirrored.
If the aspect ratios of M1 and M2, and, M3 and M4 are the same respectively, then the same current
will flow in the left and right branches (i.e. Io/2), with the sum of these currents equal to Io. Note for
accurate operation of the Op-amp, all transistors need to operate in saturation (i.e. on-resistance
remains high and mostly constant thus resulting in high gain).
Fig. 1: Circuit design of a single-stage differential CMOS Op-amp.
M1 M2
M3 M4
Mo Mbias
Ibias Vo
VDD
VSS
Vin1 Vin2
Io
ELEC372/472 – Assignment 3 3
Typically, the gain obtained from an Op-amp designed using a CMOS technology tends to be lower
compared to that developed using bipolar technology. The gain of the CMOS Op-amp can be
improved by adding an amplifiers stage such as the common-source stage shown in Fig. 2. Here, the
output from the first differential amplifier stage is connected to the second common-source amplifier
stage, comprising of a pMOST, Mop. The nMOST, Mon is also added and connected to point X. The
stability of such an amplifier can also be enhanced by introducing a compensation capacitor (Cc),
which is connected between the outputs of the differential and common-source amplifier stages. The
value of CC depends on the required phase margin and is typically smaller than CL. For example, for
a phase margin of 60o
, we can assume, ≥ 0.22
.
Fig. 2: Circuit design of a two-stage CMOS Op-amp consisting of a differential stage, common-source stage
and compensation capacitor.
The design and simulations of the Op-amp (both single and two stages) will utilise the 1.2 μm CMOS
technology on Multisim. With such long channels, we can assume the channel modulation, is
negligibly small, and thus utilise the standard saturation drain current model. The respective SPICE
and design parameters are as specified in Table 1 in Appendix A1, and the design procedures are
provided in Appendix A2.
M1 M2
M3 M4
Mo Mbias
Ibias
VDD
VSS
Vo
Cc
Mop
Mon
X
Connected
to X
Io
ELEC372/472 – Assignment 3 4
Section 1 – Design and investigate the DC, AC and transient responses of a single-stage
Op-amp by simulation and analysis
Design and simulate the single-stage Op-amp in Fig.1 with a voltage gain, Av of greater 100 ( 40
dB), gain-bandwidth product GB of 1 MHz and phase margin of 60o
(at unity gain or 0 dB).
a) Calculate the aspect ratios of all transistors (i.e. M1, M2, M3, M4, Mo, and Mbias) in the design.
Make sure to represent these as a whole number of m.
b) Build and simulate the circuit design on Multisim, and obtain the corresponding DC, AC (i.e.
Bode and phase plots) and transient (i.e. slew rate, rise/fall edge) responses.
c) Analyse the responses obtained in b), and extract/examine the key parameters from the
characteristics including gain, gain-bandwidth and phase-margin etc. Compare and comment
on the outputs obtained from the simulations to those provided in the specifications.
d) Further, optimise your design, and show how the gain and gain-bandwidth may be improved
using this design architecture.
Section 2 – Design and investigate the DC, AC and transient responses of a two-stage
Op-amp with compensating capacitor by simulation and analysis
Design and simulate the two-stage stage Op-amp in Fig. 2, consisting of an additional common source
stage and a compensating capacitor, to operate with a gain, Av of greater than 1000 (≥ 60 dB), gain bandwidth, GB of 5 MHz, and phase margin of greater than 60o
.
a) Calculate the aspect ratios of all transistors (i.e. M1, M2, M3, M4, Mo, Mbias, Mop, and Mon)
in the design. Make sure to represent these as whole multiple of m.
b) Build and simulate the circuit design on Multisim, and obtain the corresponding DC, AC (i.e.
Bode and phase plots) and transient (i.e. slew rate, rise/fall edge) responses.
c) Analyse the responses obtained in b), and extract/examine the key parameters from the
characteristics including gain, gain-bandwidth and phase-margin etc. Compare and comment
on the outputs obtained from the simulations to those provided in the specifications.
d) Further, optimise your design, and show how the gain and gain-bandwidth may be improved
using this design architecture. Comment on the significance of the compensating capacitor.
ELEC372/472 – Assignment 3 5
Section 3 – Investigate amplifier circuits with closed loop gain
In Sections 1 and 2 we investigated the open loop gain of an operational amplifier. In practical
applications, operational amplifiers are rarely used as open-loop circuits but is negative feedback to
control the gain of the circuit.
a) Briefly explain how negative feedback is used to control gain in operational amplifiers.
b) Modify the circuit from section 1 to build and simulate the circuit design on Multisim, which
uses negative feedback to create gains between -0.1 and -1000, and thus obtain the
corresponding DC, AC (i.e. Bode and phase) plots. Explain your circuit and discuss the
results. (You probably want to use ‘parameter sweeps’ to automate this – See MultiSim
guidance for details).
c) Modify the circuit from section 2 to build and simulate the circuit design on Multisim, which
uses negative feedback to create gains between -0.1 and -1000 and thus obtain the
corresponding DC, AC (i.e. Bode and phase) plots. Explain your circuit and discuss the
results. Compare with the results from section 3b.
d) Modify the circuit from sections 1 and 2 to build and simulate the circuit design on Multisim,
which uses negative feedback to create non-inverting gains between +0.1 and +1000 and
obtain the corresponding DC, AC (i.e. Bode and phase plots). Explain your circuit and discuss
the results. Compare with the results from sections 3b and 3c.
ELEC372/472 – Assignment 3 6
Appendix A1: Input/output specifications
Table 1 provides the input parameters and design specifications to be utilised in the design of the
Op-amp following the procedures in Appendix A2.
Parameter Definition Value
m (μm) CMOS Technology (minimum feature size) 1.2
VDD / VSS (V) Supply rails 5
VTp (V) Threshold voltage of pMOST 0.91
VTn (V) Threshold voltage of nMOST 0.79
Kp (A/V2
) Transconductance parameter of pMOST 2.94 × 10-5
Kn (A/V2
) Transconductance parameter of nMOST 9.64 × 10-5
CL (pF) Load capacitance 20
CC (pF) Compensation capacitance 5
SR (V/μsec) Slew rate 5
ICMR(+) (V) Maximum input voltage 4.5
ICMR( ) (V) Minimum input voltage 0.5
Pdiss (mW) Power dissipation 1
Table 1: SPICE and Design Parameters.
ELEC372/472 – Assignment 3 7
Appendix A2: Design procedure of a single-stage Op-Amp
The design procedure for the single-stage Op-Amp is provided below:
1. Determine the value of Io to satisfy the provided slew rate (SR) for a known load capacitance
(CL) and power dissipation (Pd). In Fig. 1, consider a load capacitor (CL) connected at the output,
charging through M4. The charging current can be given as,

= =

Or,

=

Thus, the rate of change in the output voltage Vo or the slew rate, SR (i.e. maximum rate of change of
voltage at the output) is given as,
=

=

Or,
= ×
Here Io is the DC current needed to bias the circuit i.e. flowing through Mo. Note, the current flowing
through the left and right branches of the differential amplifier in Fig.1 is given as (

2
) respectively,
if the aspect ratios of M1 and M2, and, M3 and M4 are matched respectively.
The power dissipation can also be determined as:
= ( + | |)
ELEC372/472 – Assignment 3 8
2. Determine the aspect ratios of M1 and M2 to satisfy the required gain-bandwidth product.
Consider the small-signal circuit of one half of differential amplifier circuit e.g. right-hand side in
Fig. 1 as shown below.
Here, ron2 and ron4 are the on-resistances of M2 and M4 connected in parallel and CL is the load
capacitance. The voltage gain is given as,

2
=
1,2
( 2// 4
)
1 + 2
( 2// 4
)
This is a single-pole system with DC gain, Av and pole, P1 given as,
= 1,2
( 2// 4
)
1 =
1
( 2// 4
)
The gain-bandwidth product is given as,
= × 1
Or alternatively substituting the above expressions results in,
=
1,2
2π
Using this expression, the value of gm1,2 can be determined for the required GB and CL provided.
Following on this, the aspect ratio of M1 (and M2) can be calculated using the expression below,
(

)
1
=
1,2
2
2 1 1
,2
Note: =

and using the saturation drain current expression, the above equation can
be derived.
Vin2 Vo
CL ron4 // ron2 gm2Vin2
ELEC372/472 – Assignment 3 9
3. Determine the aspect ratios of M3 and M4 to satisfy
the maximum input voltage, ICMR(+). Consider one half of
the differential circuit i.e. left-hand side in Fig. 1 as shown on
the side. To ensure M1 is saturated, we require,
1 ≥ 1 1
Or,
( 1 2
) ≥ ( 1( ) 2) 1
1 ≥ 1( )
Where Vin1(max) is the maximum input voltage or ICMR(+) and VTn is the threshold voltage of M1. This
allows the value of Vx1 (or the drain voltage of M3) to be determined. Subsequently, the value of
VDSM3 (or VGSM3) of M3 can be calculated. Following on this, using the appropriate current expression,
the aspect ratio of M3 (and M4) can be determined. Note, the value of the current flowing in half of
this branch is
2
.
4. Determine the aspect ratio of Mo and Mbias to
satisfy the lower input voltage, ICMR( ) or Vin1(min).
Consider the part of the circuit shown on the side where
VDSMo is the drain-source voltage of Mo in saturation and
VGSM1 is the gate-source voltage of M1 given as,
1 = 1( )
Using appropriate drain current expression and aspect ratio
for M1 obtained in part 2) above, initially determine the
value for VGSM1. Note the current through M1 is
2
. Subsequently, work out the value of VDSMo using
the above expression, assuming the given minimum input voltage. Note this could be a negative
voltage value. Following on this, using the appropriate drain expression for Mo, work out its aspect
ratio, assuming VDSMo = VGSMo VT.
5. Simulate your design. If required, iterate the process so as to optimise the design and attain
the required gain and gain bandwidth.
M1
M3
VDD
Vin1 (max)
Vx1
Io
Vx2
M1
Mo
Vin1 (min)
Io
/2
VDSMo(sat)
VGSM1
Io
ELEC372/472 – Assignment 3 10
Appendix A3: Design procedure of a two-stage Op-Amp
The design procedure for the two-stage Op-Amp is provided below:
1. Determine the value of Io to satisfy the slew rate (SR) for a known value of compensating
capacitance (Cc) as given by expression below.
= ×
2. Determine the aspect ratios of M1 and M2 to satisfy the required gain-bandwidth product.
The small-signal circuit of the two-stage amplifier is shown below. For simplicity, we can consider
each amplifier stage separately, such that gm1Vin, C1 and r1 relates to the 1st stage amplifier, whilst
gm2Vx, C2 and r2 relates to the 2nd stage amplifier. Here, Vx is the output from the first stage into the
second stage amplifier.
The DC gain of the two-stage amplifier can be given as,
= 1 1 × 2 2
Note this is a two-pole system with respective poles given as,
1 = 2
1
1 2
and 2 =
2
2
The gain-bandwidth product is given as,
= × 1
Substituting the above expressions, we find,
=
1
2π
Cc
Vi n Vo C2
r1 gm1Vi n C1
gm2Vx r2
Vx
ELEC372/472 – Assignment 3 11
Using this expression, the value of gm1 can be determined assuming the respective values of GB and
Cc provided. Following on this, the aspect ratio of M1 (and M2) can be calculated using the expression
below:
(

)
1
=
1
2
2 1
3. Determine the aspect ratios of M3 and M4 to satisfy
the maximum input voltage, ICMR(+) or Vin1(max). Consider
half of the differential circuit as shown in the circuit. To ensure
M1 operates in saturation, we require,
1 ≥ 1 1
Or 1( ) ≤ ( 1 + 1
)
Here Vin1(max) is the maximum input voltage ICMR(+). Vx1(min)
needs to be determined, which can be done by determining the
current in M3. Note M3 is operating in saturation since its gate is tied to its drain, such that,
1( ) = 3
Using the drain current expression, we can express VGSM3 as below,
3 = √
2 3
(

)
3
+ 3
And substituting this to the equation above, we find,
1( ) =
[

√
2 3
(

)
3
+ 3
]

Substituting this expression above and rearranging, we obtain expression below, which can used to
determine the aspect ratio of M3.
(

)
3
=
2 3
( (+) 3 + 1 )
2
M1
M3
VDD
Vin1 (max)
Vx1
Io
Vx2
ELEC372/472 – Assignment 3 12
4. Determine the aspect ratio of Mo and Mbias to
satisfy the lower input voltage, ICMR( ) or Vin1(min).
Consider the part of the circuit shown on the side where
VDSMo is the drain-source voltage of Mo in saturation and
VGSM1 is the gate-source voltage of M1. To ensure that Mo
remains in saturation, we need to maintain a VDSMo(sat)
value such that,
Note,
1( ) ≥ 1 + ( )
1 = √
2 1
(

)
1
+ 1
Substituting this in the above expression, we can find the expression for VDSMo(sat) as given below,
and subsequently its corresponding value can be calculated. Note this could be a negative voltage
value.
( ) ≥ 1( ) √
2 1
(

)
1
1
And using the current expression below, the aspect ratio of Mo can be determined. Here IDsatMo is
equal to Io in the circuit diagram.
=

2

(

)

( )
2
5. Determine the aspect ratio of Mop for the required phase margin, such that we can assume that,
Mop ≥ 10 1
And if M3 and M4 are matched correctly, then we can assume the corresponding VGS and VDS are the
same to that of Mop. In this case, the difference in these devices are their respective aspect ratios,
which subsequently determines the current flowing through them. Thus, we can represent the ratios
as given in the expression below,
M1
Mo
Vin1 (min)
Io
/2
VDSMo(sat)
VGSM1
Io
ELEC372/472 – Assignment 3 13
(
(

)
)

4
=

4
Or,
(
(

)
)

4
=

4
Using this expression, the aspect ratio of Mop can be calculated.
6. Determine the aspect ratio of Mon. Consider part of the circuit as shown,
the same current, IDMop is flowing in Mop and Mon. Using the same
expression above, we can find the value of the current, IDMop such that,
=
(
(

)
)

4
4
Similarly, if the devices are matched appropriately then the VDS and VGS of
Mo and Mon are the same, such that,
(
(

)
)

=

Thus, the aspect ratio of Mon can be determined.
7. Iterate and optimise the design, if needed, to attain the required gain and gain bandwidth from the
simulations.
Mop
Mon
IDMop